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Switches in a network should be compliant with the specification developed by Time-Sensitive Networking Task Group (TSN-TG) to be able to provide the above mentioned protocols. The architectural model of a 802.1Qbv compliant switch is depicted in figure 4. Each port in the switch has eight queues, a transmission gate for each queue and a programmable gate driver. An incoming frame is processed by the switch and classified as one of the following traffic classes, scheduled traffic, credit-based queue (CBQ) and other types of traffic. These traffic classes are uniquely identified by 3 bit (VLAN) tag encoded priority values and are assigned to separate queues. A traffic class is allowed to access the transmission medium only if the transmission gate of the queue it is assigned to is open. The gate opening event allows the transmission of a queued frame and the gate closing event terminates the access to the medium. These events are controlled by the gate driver program. The gate driver program is a set of SetGateStates operations. Each operation consists of a time delay parameter and GateState parameter. The time delay parameter indicates the duration between the execution of the current gate operation and the subsequent one. The GateState is an eight bit vector, each bit representing the state (Open or close) of each gate. These GateState operations are set according to the transmission schedule. As it is evident, IEEE 802.1Qbv compliant Switch provides some degree of protection for “time-sensitive traffic” against interference caused by traffic with less stringent timing requirements. This means that the delay through each switch is deterministic and the message latency through a network of TSN-enabled components can be guaranteed.

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